Future mobile terminals such as smart phones and tablet computers will require simultaneous transmission of signals on two different frequencies that are referred to as multi-carriers. A relatively large bandwidth for the multi-carriers is on the order of 20 MHz each. A separate power amplifier (PA) is needed for each of the multi-carriers. FIG. 1 is a schematic for a related art dual charge-pump converter 10 that is usable to supply power to a first power amplifier (PA) 12 and a second PA 14. The related art dual charge-pump converter 10 includes a first charge pump CP#1 and a second charge pump CP#2 that present a disadvantage in that relatively expensive and area consuming components are duplicated for each of the first PA 12 and the second PA 14.
FIG. 2 is a circuit diagram for a related art charge pump 16 of the single phase type. The charge pump 16 includes a capacitor C1 having a first electrode 18 and a second electrode 20. A first switch SW1 has a first terminal 22 coupled to a high voltage node 24, a second terminal 26 coupled to the first electrode 18 of the capacitor C1, and a control terminal 28 for receiving a first control signal S1. A second switch SW2 has a first terminal 30 coupled to the first electrode 18 of the capacitor C1, a second terminal 32 that is adapted to be an output LX, and a control terminal 34 for receiving a second control signal S2. A third switch SW3 has a first terminal 36 coupled to the high voltage node 24, a second terminal 38 coupled to the second electrode 20 of the capacitor C1, and a control terminal 40 for receiving a control signal S3. A fourth switch SW4 has a first terminal 42 coupled to the second electrode 20 of the capacitor C1, a second terminal 44 coupled to a low voltage node 46, and a control terminal 48 for receiving a fourth control signal S4. The high voltage node 24 is typically held at a battery voltage VBAT, while the low voltage node 46 is typically at ground potential.
FIG. 3 is a timing diagram for the control signals S1, S2, S3 and S4 needed for the related art charge pump 16 to output a voltage at the output LX. The timing diagram begins at a time t0 with the control signals S1 and S4 at logic low (L) and the control signals S2 and S3 at logic high (H). As a result, the first switch SW1 and the fourth switch SW4 are non-conducting while the second switch SW2 and the third switch SW3 are conducting. Thus, the voltage VBAT is applied to the second electrode 20 of the capacitor C1 while the first electrode 18 of the capacitor C1 is effectively coupled to the output LX. Therefore, assuming that the capacitor C1 is charged to the voltage VBAT from a previous cycle, the voltage at the output LX will be two times VBAT.
After a predetermined time t1, the control signals S1 and S4 transition to logic high while the control signals S2 and S3 transition to logic low. At this point, the first switch SW1 and the fourth switch SW4 are conducting while the second switch SW2 and the third switch SW3 are non-conducting. In this way, the first electrode 18 of the capacitor C1 is effectively coupled to the high voltage node 24 and the second electrode 20 of the capacitor C1 is effectively coupled to the low voltage node 46. As a result, the capacitor C1 is charged to the value of VBAT, which is the voltage applied to the high voltage node 24. After a predetermined time t2 of charging, a new cycle begins by transitioning the control signals S1 and S4 from logic high back to logic low while the control signals S2 and S3 transition from logic low back to logic high.
FIG. 4 is a circuit diagram for a related art dual phase charge pump 50. The dual phase charge pump 50 combines the charge pump 16 with a charge pump 52. The charge pump 52 includes a capacitor C2 having a first electrode 54 and a second electrode 56. A fifth switch SW5 has a first terminal 58 coupled to the high voltage node 24, a second terminal 60 coupled to the first electrode 54 of the capacitor C2, and a control terminal 62 for receiving a fifth control signal S5. A sixth switch SW6 has a first terminal 64 coupled to the first electrode 54 of the capacitor C2, a second terminal 66 coupled to the output LX, and a control terminal 68 for receiving control signal S6. A seventh switch SW7 has a first terminal 70 coupled to the high voltage node 24, a second terminal 72 coupled to the second electrode 56 of the capacitor C2, and a control terminal 74 for receiving a control signal S7. An eighth switch SW8 has a first terminal 76 coupled to the second electrode 56 of the capacitor C2, a second terminal 78 coupled to the low voltage node 46, and a control terminal 80 for receiving a control signal S8.
FIG. 5 is a timing diagram for the control signals S1 through S8 needed for the related art charge pump 50 (FIG. 4) to output a voltage at the output LX. The timing diagram begins a cycle at time t0 with the control signals S1, S4, S6, and S7 at logic low (L) and the control signals S2, S3, S5, and S8 at logic high (H). Thus, the first switch SW1 and the fourth switch SW4 are non-conducting while the second switch SW2 and the third switch SW3 are conducting. As a result, the voltage VBAT is applied to the second electrode 20 of the capacitor C1 while the first electrode 18 of the capacitor C1 is effectively coupled to the output LX. Therefore, assuming that the capacitor C1 is charged to the voltage VBAT from a previous cycle, the voltage level at the output LX will be at a voltage level that is two times VBAT. Moreover, the fifth switch SW5 and the eighth switch SW8 are conducting while the sixth switch SW6 and the seventh switch SW7 are non-conducting. As a result, the first electrode 54 of the second capacitor C2 is effectively coupled to the high voltage node 24, while the second electrode 56 is effectively coupled to the low voltage node 46. In this way, the second capacitor C2 is charging to the voltage VBAT while the first capacitor C1 is discharging.
At a first predetermined time t1, the control signals S2 and S2 transition to logic low. As a result, the second switch SW2 and the third switch SW3 become non-conducting. The second terminal 32 of the second switch SW2 is left floating as shown with an exponentially decaying dashed line between pulses of voltage at the LX node. Simultaneously, the control signals S1 and S4 transition to a logic high. In this way, the first electrode 18 of the first capacitor C1 will be effectively coupled to the high voltage node 24 and the second electrode 20 will be effectively coupled to the low voltage node 46. As a result, the first capacitor C1 begins charging to the voltage VBAT.
At a second predetermined time t2, the control signals S5 and S8 transition to logic low. In this way, the switches SW5 and SW8 become non-conducting. Simultaneously, the control signals S6 and S7 transition to logic high. As a result, the voltage VBAT is applied to the second electrode 56 of the capacitor C2 while the first electrode 54 of the capacitor C2 is effectively coupled to the output LX. Therefore, assuming that the capacitor C2 is charged to the voltage VBAT, the voltage level at the output LX will be at a voltage level that is two times VBAT. The cycle repeats at a third predetermined time t3.
The related art charge pump 16 (FIG. 2) and the related art charge pump 50 (FIG. 4) are both suitable as the first charge pump CP#1 (FIG. 1) and the second charge pump CP#2 (FIG. 2) for the related art dual charge-pump converter 10. However, neither the related art charge pump 16 nor the related art charge pump 50 can alone replace the related art dual charge-pump converter 10. What is needed is a single charge pump that generates independent voltage levels thereby fulfilling the role of the related art dual charge-pump converter 10.